1. Technical Field
Various embodiments of the present disclosure generally relate to a semiconductor integrated circuit, and more particularly, to a semiconductor memory apparatus and a test method using the same.
2. Related Art
FIG. 1 is a diagram schematically showing a configuration of a typical semiconductor memory apparatus with an open bit line structure. As shown in FIG. 1, the typical semiconductor memory apparatus with the open bit line structure comprises a first memory cell 10, a second memory cell 20, a bit line equalization unit 30, a sense amplifier 40, a voltage supply unit 50, and a data transfer unit 60.
The first memory cell 10 comprises a first transistor N1 and a first capacitor C1. When a first word line WL1 is enabled, the semiconductor memory apparatus may store data in the first memory cell 10 by charging/discharging electric charges to/from the first capacitor C1 through a first bit line BL1.
Similarly, the second memory cell 20 comprises a second transistor N2 and a second capacitor C2. When a second word line WL2 is enabled, the semiconductor memory apparatus may store data in the second memory cell 20 by charging/discharging electric charges to/from the second capacitor C2 through a second bit line BL2.
The bit line equalization unit 30 comprises third to fifth transistors N3 to N5. The bit line equalization unit 30 precharges the first and second bit lines BL1 and BL2 to a bit line precharge voltage (VBLP) level if a bit line equalization signal BLEQ is enabled.
The sense amplifier 40 comprises sixth to ninth transistors P1, P2, N6 and N7. The sense amplifier 40 receives a voltage of a first node A_node and a voltage of a second node B_node, and senses and amplifies a voltage level difference between the first and second bit lines BL1 and BL2.
The voltage supply unit 50 comprises tenth to fifteenth transistors N8 to N13. The voltage supply unit 50 applies a core voltage Vcore or an external voltage VDD to the first node A_node in response to first and second voltage supply signals SAP1 and SAP2, and applies a ground voltage VSS to the second node B_node in response to a third voltage supply signal SAN. In addition, the voltage supply unit 50 precharges the first and second nodes A_node and B_node to the bit line precharge voltage (VBLP) level if the bit line equalization signal BLEQ is enabled.
The data transfer unit 60 comprises sixteenth and seventeenth transistors N14 and N15. The data transfer unit 60 transfers data of the first and second bit lines BL1 and BL2 to first and second data transfer lines LIO and LIOB when a column selection signal YS is enabled.
To improve reliability of the semiconductor memory apparatus, a test is typically performed to determine whether or not leakage current has occurred between a word line and a bit line. This test is referred to as an Unlimited Sensing Delay (USD) test, in which the occurrence of leakage current between the word line and the bit line serves as a criterion on how long data stored in the memory cell will be retained.
In the USD test, the semiconductor memory apparatus stores a logic low data in the memory cell, and then enables the word line for a predetermined time. When the predetermined time elapses, the semiconductor memory apparatus performs a read operation to output the stored data. When leakage current has occurred between the word line and the bit line, a logic high data is output, whereas, when no leakage current has occurred, a logic low data is output. The longer the test time between when the word line is enabled and when the read operation is conducted, the higher is the reliability of the USD test.
However, the typical semiconductor memory apparatus with the open bit line structure cannot increase a test time of the USD test due to leakage current of a transistor. This is because in the USD test, since only the first word line WL1 is enabled and the first to third power supply signals SAP1, SAP2 and SAN are all disabled, both the first and second nodes A_node and B_node change to a floating state.
Leakage current of the twelfth transistor N10, which is configured to apply the ground voltage VSS to the second node B_node, is greater than a sum of leakage current of the tenth and eleventh transistors N8 and N9, which are respectively configured to apply the external voltage VDD and the core voltage Vcore to the first node A_node. That is, the amount of leakage current flowing out from the sense amplifier 40 is greater than the amount of leakage current flowing into the sense amplifier 40. In addition, the eighth and ninth transistors N6 and N7, which are respectively coupled to the first and second bit lines BL1 and BL2, also generate leakage current to the second node B_node.
When, in the USD test, the semiconductor memory apparatus enables the first word line WL1 and generates a voltage level difference between the first and second bit lines BL1 and BL2, the voltage levels of the first and second bit lines BL1 and BL2 are continuously decreased as the USD test time is increased.
Consequently, as the USD test time is increased, the voltage level difference between the first and second bit lines BL1 and BL2 is decreased. When the voltage level difference between the first and second bit lines BL1 and BL2 is decreased, the sense amplifier 40 cannot perform the sense amplification operation normally. Accordingly, the USD test time cannot be increased due to the leakage current of the transistor, and the reliability of the USD test cannot be improved.